基于Verilog的简单FIFO读写实验

一、模块框图及基本思路

fifo_ip:ISE生成的IP

fifo_control:在fifo未满情况下不断写入递增的四位数，每隔1s读出一个数据驱动Led显示

fifo_top:前两个模块的组合

二、软件部分

fifo_control:

 module fifo_control(
     clk,rst,
     Data_Out,
     din,wr_en,full,
     dout,rd_en,empty
     );
      input clk,rst;
      output[:] Data_Out;
      output [:] din;  //相对fifo来说是输入
      input [:] dout;  //相对fifo来说是输出
      output wr_en,rd_en;
      input full,empty;     /****************定时部分*********************/
     localparam T1S=50_000_000-;
     reg[:] Count_1s;
     always @(posedge clk or posedge rst)
     begin
         if(rst)
         begin
             Count_1s<='d0;
         end
         else if(Count_1s==T1S)
             Count_1s<='d0;
         else if(!isCount)
             Count_1s<='d0;
         else Count_1s<=Count_1s+'b1;
     end
     /*****************FIFO写入部分********************/
     reg [:] i;
     reg wr_en;
     reg [:]din;     always @(posedge clk or posedge rst)
     if(rst)
     begin
         din<='d0;
         i<='d0;
         wr_en<='b0;
     end
     else if(!full)
     case(i)
         'd0:begin din<=din+1'b1;i<=i+'b1;wr_en<=1'b1;end
         'd1:begin i<=2'd0;wr_en<='b0;end
     endcase
     /*******************FIFO读出部分***************************/
     reg[:] Data_Out_r;
     wire [:] dout;
     reg isCount;
     reg [:]j;
     reg rd_en;     always @(posedge clk or posedge rst)
     if(rst)
     begin
         Data_Out_r<='d0;
         j<='d0;
         isCount<='b0;
         rd_en<='b0;
     end
     else if(!empty)
     case(j)
         'd0:if(Count_1s==T1S) begin j<=j+1'b1;isCount<='b0;rd_en<=1'b1;  end
                 else isCount<='b1;
         'd1:begin rd_en<=1'b0;j<=j+'b1;end
         'd2:begin Data_Out_r<=dout;j<=3'd0; end
     endcase
     assign Data_Out=Data_Out_r;     /****************************************************/ endmodule

fifo_top:

 module fifo_top(
     clk,RSTn,
     Data_Out
     );
      input clk,RSTn;
      output[:] Data_Out;      wire [:]din;
      wire [:]dout;
      wire wr_en,rd_en,full,empty;     /****************************************************/
     fifo_ip U0 (
   .clk(clk), // input clk
   .rst(!RSTn), // input rst
   .din(din), // input [3 : 0] din
   .wr_en(wr_en), // input wr_en
   .rd_en(rd_en), // input rd_en
   .dout(dout), // output [3 : 0] dout
   .full(full), // output full
   .empty(empty) // output empty
 );
     /*********************************************************/
     fifo_control U1 (
         .clk(clk),
         .rst(!RSTn),
         .Data_Out(Data_Out),
         .din(din),
         .wr_en(wr_en),
         .full(full),
         .dout(dout),
         .rd_en(rd_en),
         .empty(empty)
     );  endmodule

三、硬件部分

黑金SPARTAN开发板

 NET "clk" LOC = T8;
 NET "RSTn" LOC = L3; NET "Data_Out[0]" LOC = P4;
 NET "Data_Out[1]" LOC = N5;
 NET "Data_Out[2]" LOC = P5;
 NET "Data_Out[3]" LOC = M6;